1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to external event control.
2. Description of Related Art
Delivering an external architectural events in a precise manner is a non-trivial task. The problem is even more compounded for modern microprocessors because of their internal complexities. Modern microprocessors typically have multiple pipeline stages, out-of-order execution, multiple bus fractions for external and internal buses. Generating an external stimulus, or event, to hit a specified instruction boundary in these modern microprocessors is extremely difficult.
The basic problem with injecting external events to the processor is the difficulty in maintaining the synchronism between the external event and the flow of the pipeline. One traditional technique attempts to synchronize the external event with the end of macro (EOM) by introducing no-operation (NOP) micro-operations (micro-ops). This technique requires extensive engineering time for tuning to accommodate different bus speeds. Another technique uses a pounding mechanism to manipulate the valid bit in the re-order buffer (ROB) in order to allow the event to arrive from the pin to the core. However, this technique adds artificial states to the core.
Therefore there is a need in the technology to provide a simple and efficient method to injecting external events to the processor core.
The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match between the target instruction address and a pipeline instruction pointer corresponding to a second pipeline stage. The second pipeline stage is earlier than the first pipeline stage in the pipeline chain. The external event is unmasked via a delivery path between a signal representing the asserted external event and the first pipeline stage.